Voltage reference circuit using PTAT voltage

ABSTRACT

A voltage reference generator is disclosed that includes a current generator for generating a current that is proportional to absolute temperature (PTAT), the current generator having an internal resistance. This provides a PTAT current that is proportional to the resistance and wherein the temperature coefficient of the PTAT current is defined by the resistance. An output node is driven by the current generator with the PTAT current. A stack of serial connected MOS devices is connected between the output voltage and a ground reference voltage. The stack of transistors has a transimpedance associated therewith which has a temperature coefficient that is opposite in polarity to the temperature coefficient of the internal resistance and of a magnitude to provide a voltage on the output node that is substantially stable over temperature.

TECHNICAL FIELD OF THE INVENTION

The present invention relates in general to voltage references and, moreparticularly, to a voltage reference utilized in a voltage regulatorincorporating therein a low power band gap reference generator.

BACKGROUND OF THE INVENTION

Many analog circuits require voltage references, such as A/D and D/Aconverters, voltage regulators, etc. A voltage reference must be,inherently, well-defined and insensitive to temperature, power supplyand load variations. The resolution of an A/D or D/A converter, forexample, is limited by the precision of its reference voltage over thesupply voltage range of the circuit and the operating temperature rangethereof. A band gap reference voltage generator is a well utilizedcircuit that is typically used for the purpose of generating such atemperature independent reference voltage. These voltage referencesexhibit both high power supply rejection and possess a low temperaturecoefficient, and these type of voltage reference circuits are probablythe most popular high performance voltage references utilized inintegrated circuits. However, integrated circuit design is predominatedby the need for low power, low voltage operation. This inherently willlead to the need for utilizing CMOS process technology, the technologyof choice. Since the band gap reference is bipolar in nature, solutionsare required to create the reference voltage without the use of thecostly BiCMOS process. Further, for low power operation, there willtypically be provided in the band gap reference ratiometric relatedresistors. In order to provide for a low current, one of these resistorsis typically on the order of many times the size of the other resistorand this can lead to some fairly large resistors to realize the lowcurrent operation. The area required for these larger resistors is ofconcern and presents a disadvantage when considering an area efficientreference generator.

SUMMARY OF THE INVENTION

The present invention disclosed and claimed herein, in one aspectthereof, comprises a voltage reference generator. A current generator isprovided for generating a current that is proportional to absolutetemperature (PTAT), the current generator having an internal resistance.This provides a PTAT current that is proportional to the resistance anda voltage and wherein the temperature coefficient of the PTAT current isdefined by both. An output node is driven by the current generator withthe PTAT current. A stack of serial connected MOS devices is connectedbetween the output voltage and a ground reference voltage. The stack oftransistors has a transimpedance associated therewith and which has atemperature coefficient such that, when combined with the PTAT generatedcurrent, provides a voltage on the output node that is of sufficientmagnitude and substantially stable over temperature.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and theadvantages thereof, reference is now made to the following descriptiontaken in conjunction with the accompanying Drawings in which:

FIG. 1 illustrates a diagram for a regulator for receiving input voltageand providing an output regulated voltage and having an internalreference thereto;

FIG. 2 illustrates a schematic diagram of a prior art band gapgenerator;

FIG. 3 illustrates a schematic diagram of the reference generator of thepresent disclosure for generating the internal reference voltage.

FIG. 4 illustrates a schematic diagram for the output reference device;

FIG. 5 illustrates a schematic diagram for the variable lengthdiode-connected n-channel transistor in the output reference circuit;

FIG. 6 illustrates a schematic diagram of the linear n-channel variablelength transistor in the output reference circuit; and

FIG. 7 illustrates a top view of the structure of the variable lengthtransistors.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to FIG. 1, there is illustrated a diagram for a voltageregulator. The voltage regulator basically is comprised of a p-channelpass transistor 102 having the source/drain thereof connected between aninput voltage on node 104 and a regulated output voltage on output pad106. The output regulated voltage on the output pad 106 drives theon-chip circuitry associated therewith (not shown). This is theregulated voltage output. The gate of the transistor 102 is driven by anamplifier 108 that provides the regulating voltage. The negative inputof amplifier 108 is connected to a node 110. Node 110 has a currentdriven thereto by a current source 112 connected between the supplyvoltage and node 110 for driving a reference load device 114. Thereference load device 114 will be described in detail herein below. Thecurrent source 112 provides a current that is a Proportional To AbsoluteTemperature (PTAT) current. This current has a Positive TemperatureCoefficient (PTC) and the reference load 114 will have a counteractingNegative Temperature Coefficient (NTC), so as to provide an overall zerotemperature coefficient (ZTC) output on node 110. In general, thecurrent source 112 and output reference load 114 provide a voltagecircuit.

The positive input of the amplifier 108 is connected to a node 116. Node116 is also connected to one side of a current sink 119 to ground. Theamplifier 108 will compare this voltage on node 116 with the voltage onnode 110 and adjust the voltage on the gate of transistor 102 such thatthe voltage on node 106 is regulated to that on the reference node 110.Note that this is a fairly conventional regulator circuit with theexception of the way in which the reference voltage on node 110 isgenerated.

Referring now to FIG. 2, there is illustrated a schematic diagram of aconventional prior art band gap generator. These type of band gapgenerator circuits are well known in the art. A first PNP transistor 202is connected between a node 204 and ground with the emitter thereofconnected to node 204 and the collector thereof connected to ground. Thebase thereof is connected to ground. As such, transistor 202 appears asa diode. A second PNP transistor 203 is connected between a node 206 andground with the emitter thereof connected to node 206 and the collectorthereof connected to ground. The base of transistor 203 is connected toground and, therefore, it is configured as a diode between node 206 andground. A resistor 208 is connected between node 206 and a node 210. Afirst current source 212 is connected between V_(DD) and node 204 anddrives the emitter of transistor 202. A second current source 214 ismirrored with transistor 212 and is connected between V_(DD) and node210 and drives the resistor 208 and transistor 203. An operationalamplifier 216 has one input thereof connected to node 210 and one inputthereof connected to node 204. The output of operational amplifier 216is operable to vary the currents through current sources 212 and 214.

An output leg is provided with a PNP transistor 218 connected between anode 220 and ground, the emitter thereof connected to node 220 and thecollector thereof connected to ground. The base thereof is connected toground also. This is a diode configured transistor. A resistor 222 isconnected between an output node 224 and node 220. A third currentsource 226 is connected between V_(DD) and node 224 and drives thecurrent thereto. For discussion purposes, transistor 202 will be labeledQ1, transistor 203 labeled Q2, resistor 208 labeled R1 and resistor 222labeled R2. The voltage on the node 224 is defined as:$V_{ref} = {V_{EBQ3} + {\frac{R_{2}}{R_{1}}V_{T}\quad{\ln\left( \frac{A_{1}}{A_{2}} \right)}}}$This is a well understood equation and is found in most text books onthe subject matter.

Both of the resistors 208 and 222 have a Positive TemperatureCoefficient (PTC). If resistor 222 were the same value as resistor 208,then the variation with respect to temperature would be the same. Tominimize this, it is typical to increase the size of resistor 222relative to that of resistor 208 such that resistor 222 is on the orderof approximately five times the size of resistor 208. However, it can benoted that the drop across the emitter-base junction of transistor 218will be 0.7V and this is defined by the physics of the semiconductordevice. This is fairly constant even through process variations. ThePTAT current flowing through resistor 222 is ratiometrically related tothe current flowing through resistor 208. By increasing the size ofresistor 222 relative to resistor 202, the PTC is amplified. Forexample, the emitter-based junction of transistor 218 or the diodeprovided thereby has a Negative Temperature Coefficient (NTC) ofapproximately −2 mV/1C. The voltage I-R using resistor 206 has atemperature coefficient of +0.5 mV/° C., such that four resistors thesize of resistor 206 that would comprise resistor 222 would result in a+2.0 mV/° C. PTC. This would offset the temperature coefficient of thediode 218 and would provide a temperature stable output voltage on node224. Again, this is a conventional operation.

For low current operations, it is desirable to minimize the amount ofcurrent that flows through resistor 208 and resistor 222. If resistor208 is increased in size, since the diode in transistor 203 has arelatively fixed voltage there across, then a much lower current can beprovided. However, this then requires that resistor 222 to be muchlarger. The problem this presents in a low current operational mode isthat the resistors become very large and can occupy a large amount ofarea. For example, for a low current operation, the resistor 208 mightbe of the size 127 kilo-ohms and the resistor 222 could be on the orderof 522 kilo-ohms. These are very large resistors and take up a lot ofarea and are not very area efficient.

Referring now to FIG. 3, there is illustrated a schematic diagram of thevoltage reference circuit of the present disclosure with an areaefficient output load device which is comprised of a stack of saturatedand linear devices with a PTAT current flowing there through. Ann-channel transistor 302 has the source/drain path thereof connectedbetween a node 304 and ground, the gate thereof connected to node 304. Asecond n-channel transistor 306 has the source/drain path thereofconnected between a node 308 and a node 310. Node 310 is connected toone side of a resistor 312, the other side thereof connected to ground.Node 304 is connected to one side of the source/drain path of ap-channel transistor 314, the other side thereof connected to V_(DD).The gate of transistor 314 is connected to a node 316 with a secondp-channel transistor 318 having the source/drain path thereof connectedbetween V_(DD) and the node 308, the gate of p-channel transistor 318connected to node 316 in a diode-configured manner. In this embodiment,transistor 314 is sized at “X” and transistor 318 is sized at “2×.”Therefore, the current flowing through transistor 314 will be I₁ and thecurrent flowing through transistor 318 will be 2I₁. Thus, the currentflowing through resistor 312 will be 2I₁. The currents I₁ and 2I₁ arePTAT currents. This is sometimes referred to as a self-biased lowcurrent reference generator.

The current through transistors 314 and 318 is mirrored to a p-channeltransistor 330 having the source/drain path thereof connected betweenV_(DD) and an output node 332, the gate thereof connected to node 316.Transistor 330 is sized in the disclosed embodiment to “X” such that thecurrent there through is I₁. Node 332 is connected to one side of theoutput node reference 114 to ground. The PTAT current flowing throughthe output reference node 114 will vary over temperature, but theimpedance of the output mode reference 114 will vary as a function oftemperature to maintain the voltage on node 332 at a temperatureindependent level. This will be described in more detail herein below.As will also be described herein below, the output reference node 114 isfabricated with a stack of linear and saturated MOS devices and,therefore, will have significantly less area associated with theconstruction thereof and is easily programmed.

Referring now to FIG. 4, there is illustrated a schematic diagram of theoutput reference mode 114. There are provided four n-channel transistors404, 406, 408 and 410 connected in series between node 332 and a node412 in a stack. Transistor 404 has the source/drain path thereofconnected between node 332 and a node 414, the gate thereof connected tothe source at node 332 in a diode configuration. Transistor 406 is alsoconnected in a diode configuration with the source/drain path thereofconnected between node 414 and a node 416, the gate thereof connected tonode 414. Transistor 408 has the source/drain path thereof connectedbetween node 416 and a node 418, the gate thereof connected to node 416.Transistor 410 has the source/drain path thereof connected between node418 and node 412, the gate thereof connected to node 418. Transistors404-410 are therefore configured such that they are operating in thesaturated mode. The voltage across the source/drain path of each of thetransistors 404-410 will be the gate-to-source voltage, V_(GS), due tothe way they are connected. The transistors 406-410 are low V_(T)devices.

Each of the transistors 404-410 are operable to be switched out of thecircuit between node 332 and node 412. A first p-channel transistor 424has the source/drain path thereof connected between node 332 and node414. The second p-channel transistor 426 has the source/drain paththereof connected between node 332 and node 416. A third p-channeltransistor 428 has the source/drain path thereof connected between node332 and node 418. A fourth p-channel transistor 430 has the source/drainpath thereof connected between node 332 and node 412. The gates oftransistors 424-430 provide the signals for selecting how many and whichof the transistors 404-410 are connected in series between node 332 andnode 412.

There are provided two variable length transistor structures 432 and434, comprised of a transistor structure that effectively provides atransistor with a variable length for a given width. (It should beunderstood that the transistors could have a variable width also.) Thevariable length transistor structure 432 is connected between node 412and a node 436. The variable length transistor structure 434 isconnected between node 436 and a node 438. Each of the variable lengthtransistor structures 432 and 434 is illustrated as a transistor havingthe gate thereof connected in a diode configuration such that theyoperate in the saturated range such that V_(GS) is the voltage thereacross. Therefore, there will be a voltage V_(GS) across nodes 412 and436 and a voltage V_(GS) across nodes 436 and 438, this being varied byvarying the length of the transistor, as will be described herein below.A third variable length transistor structure 440 is provided and isdisposed between node 438 and ground. This is illustrated as atransistor with an associated gate structure that is connected to node412 and, therefore, operates in the linear region. The voltage thereacross will be the drain-to-source voltage, V_(DS). Changing the lengthof transistors 432 and 434 changes the V_(GS). Transistor operates likea linear r_(ds) resistor with a PTC. Further, each of the variablelength transistor structures 432 and 434 has the length varied therethrough for the purpose of changing the voltage on the output node 332and calibrating out process variations. By changing the length on thetransistors, there is provided an overall effect on the R of the deviceand the voltage thereacross.

Referring now to FIG. 5, there is illustrated a schematic diagram ofeither of the transistor structures 432 or 434, the transistor structure432 being illustrated. The transistor structure 432 is comprised of aplurality of n-channel transistors 444 disposed in series with basicallya common channel with the gates thereof all connected together and tothe node 412. There are provided a plurality of p-channel transistors446 that are connected between the node 412 and the source/drainjunction of select ones of the transistors 444. In one disclosedembodiment, there are provided a plurality of these transistors 444.However, some of these transistors 444 have different L/W ratios(length-to-width ratios). For example, the first three of thetransistors 444 connected to node 436 from the bottom thereof havewidths of 5 microns, but lengths of 250 microns, one micron and fivemicrons, respectively. The remaining of the transistors 444 have a widthof one micron and a length of five microns. Therefore, it can be seenthat the width of the channel for substantially all the transistors isapproximately 1 micron. The p-channel transistors 446 are configuredsuch that they selectively connect node 412 to eight (not all) of thesource/drain junctions between transistors 444. The first fivesource/drain junctions between the first and second transistors 444 fromnode 436 extending up to node 412 will be selectively connectable tonode 412 and also the eighth and twelfth source/drain junctions.

The transistor structure 434 is identical to structure 432 but connectedbetween nodes 438 and 436.

Referring now to FIG. 6, there is illustrated a schematic diagram of thevariable length transistor structure 440. There are provided a pluralityof n-channel transistors 602 connected in series between the node 438and ground with all of the gates thereof connected to node 412, suchthat, as described herein above, they operate in the linear region.There will be provided a plurality of N-channel gate transistors 604connected between select ones of the common source/drain junctionsbetween adjacent ones of transistors 602 and other ones thereof. Assuch, the transistors 604 can selectively “short-out” select ones of thetransistors 602 from the “stack.” This is in response to a temperaturecoefficient adjustment for the overall stack of transistors comprised ofthe saturated and linear operating transistors.

Referring now to FIG. 7, there is illustrated a layout for thetransistors disposed in the stack, these being adjacent transistors.There is provided a common channel region that runs along a given lengthof the semiconductor substrate. This will typically be formed in anactive region, such that a channel can be defined. Each transistor willbe defined by a source region 702 and a drain region 704, it being notedthat each of the source regions and drain regions are shared by anotheradjacent transistor, such that they are common source/drain regions.There will be a channel region 706 disposed there between, each channelregion defined by a region of active semiconductor material disposedbetween insulated regions such as field oxide insulating regions. Thesource/drain regions 702/704 are heavily diffused regions that are ofopposite conductivity to the conductivity type of the channel region.These allow for contacts from upper layers to interfaced therewith. Assuch, they may have a larger dimension than the channel region 706. Eachof the channel regions has disposed there over a gate conductor 710,which gate conductor 710 is separated from the surface of the channelregion by a layer of gate oxide. The length of the transistor is thedimension between the source/drain region 702/704. The width of thetransistor is the width of the channel region. Therefore, it can be seenthat by connecting transistors in this manner, a fairly long string ofadjacently disposed transistors can be connected together. Further, if adiode connection is required, it is only necessary for the gateconductor to be connected to the appropriate one of the associatedsource/drain regions 702/704. This connection is not shown in thisembodiment, as this merely shows the length of adjacently disposedtransistors being stringed together.

Although the preferred embodiment has been described in detail, itshould be understood that various changes, substitutions and alterationscan be made therein without departing from the spirit and scope of theinvention as defined by the appended claims.

1. A voltage reference generator, comprising: a current generator forgenerating a current that is proportional to absolute temperature(PTAT), said current generator having an internal resistance, whereinsaid PTAT current is proportional to said resistance and wherein thetemperature coefficient of said PTAT current is defined by saidresistance; an output node; said current generator for driving saidoutput node with said PTAT current; and a stack of serial connected MOSdevices connected between said output voltage and a ground referencevoltage, said stack of transistors having a transimpedance associatedtherewith which has a temperature coefficient that is opposite inpolarity to the temperature coefficient of said internal resistance andof a magnitude to provide a voltage on said output node that issubstantially stable over temperature.
 2. The voltage reference of claim1, wherein said stack of serial connected MOS devices comprises a stackof serial connected MOS transistors.
 3. The voltage reference of claim2, wherein at least a portion said MOS transistors operate in thesaturated operating region.
 4. The voltage reference of claim 2, whereinat least a portion said MOS transistors operate in the linear operatingregion.
 5. The voltage reference of claim 4, wherein the remainder ofsaid MOS transistors operate in the saturated operating region.
 6. Thevoltage reference of claim 2, and further comprising a calibrationdevice for selectively determining how many of said MOS transistors areconnected in series in said stack.
 7. The voltage reference of claim 2,wherein said stack of MOS transistors comprises: a first stack ofserially connected MOS transistors connected between said output nodeand an intermediate node; and a second stack of serially connected MOStransistors connected between said intermediate node and ground; whereinsaid MOS transistors in at least one of said first and second stacksoperates in saturation and said MOS transistors in the other of saidfirst and second stacks operates in the linear operating range.
 8. Thevoltage generator of claim 7, wherein said MOS transistors in said firststack operate in the saturated region, and having the gates thereofconnected to a voltage higher than the voltage on said intermediatenode.
 9. The voltage generator of claim 8, wherein the gates of said MOStransistors in said first stack are connected in a diode configuration.10. The voltage generator of claim 9, and further comprising a pluralityof trimming transistors connectable between the source/drain junctionsof associated select ones of said MOS transistors of said first stackand said output node to define the voltage drop there across.
 11. Thevoltage generator of claim 8, wherein said MOS transistors have thegates thereof connected to a voltage higher than the voltage of saidintermediate node.
 12. The voltage generator of claim 9, and furthercomprising a plurality of trimming transistors connectable across thesource/drain junctions of associated select ones of said MOS transistorsof said first stack to define the voltage drop there across.